1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication and design, and more particularly, to a stitched IC chip layout design structure.
2. Background Art
In the integrated circuit (IC) chip fabrication industry, circuitry is formed in a semiconductor substrate using photolithography. One challenge that faces the industry is that large circuit designs are too large to place as a whole on the reticles used in photolithography. One remedy to this issue is leveraging the redundancy within the IC chip design to break the design up into a subset of smaller unique dissected regions. When resolved in multiple regions, the dissected regions can form the completed large IC chip design on a wafer by a process commonly referred to as “stitching”. Stitching includes placing the dissected IC chip (stitched) regions onto a reticle and performing multiple exposures on the wafer in order to complete the final whole IC chip image.
In terms of an IC chip fabricator (foundry), the common way of stitching a chip design is to have a customer break their own IC chip design into smaller sub-chip dissected (stitched) regions and releasing these stitched regions to the foundry to be placed on the reticle appropriately and stitched back together. The drawbacks of this approach are that it is difficult to check the design rules required of the whole IC chip and the stitched regions. In particular, appropriate design rule checks need to be performed for the whole IC chip and all of the stitched regions separately. This task falls on the customer of the foundry. In addition, stitched regions require different checks than the full IC design, which further increases the customer's burden. Further, the design rule checking required increases the release and design phases on the order of how many stitched regions the larger IC chip is dissected into. In addition, other issues beyond design rule checking may arise based on the unique issues presented by the boundaries of the stitched regions.